17. CPU Exceptions
The boot-time vectors (when BEV = 1 in the Status register) are at uncached and unmapped addresses. During normal operation (when BEV = 0) the regular exceptions have vectors in cached address spaces; Cache Error is always at an uncached address so that cache error handling can bypass a suspect cache.
The exception vector assignments for the R10000 processor shown in Table 17-1; the addresses are the same as for the R4400.
Table 17-1 Exception Vector Addresses
